基于fpga的串口控制器设计-中英文翻译.rar

Introduction
The use of hardware description language (HDL) is becoming a more dominant factor, when designing and verifying FPGA designs. The use of behavior level description not only increases the design productivity, but also provides unique advantages in the design verification. The most dominant HDL stoday are called Verilog and VHDL. This application note will illustrate the use of Verilog in design and verification of a digital UART (Universal Asynchronous Receiver & Transmitter).



简介
使用硬件描述语言 (HDL) 设计和开发验证FPGA的成为当前的主流因素。使用行为级描述不只增加了产品的设计效率，也在设计中有独特的验证方式。目前最流行的HDL语言为Verilog 和 VHDL。 这篇文章将会举例说明用 Verilog语言 的设计和验证数字异步串行收发器UART。